1. Field of the Invention
The present invention relates to a signal processing circuit and method, and particularly, relates to a signal processing circuit and method which facilitate positional adjustment and correction processing in increments of single dots, and so forth, even in the event of employing multiple signal processing circuits as a display apparatus signal processing system.
2. Description of the Related Art
With a display apparatus in which pixels are disposed in a matrix shape, such as an active matrix type liquid crystal display (LCD), apparatus, a digital signal processing circuit (DSD (Digital Signal Driver), ID (Integrated Circuit)) made up of the MOS process of a gate array is commonly employed as the signal processing system thereof. The digital data subjected to predetermined signal processing at this digital signal processing circuit is converted into an analog signal by an S/H (Sample/Hold) driver or the like, and then supplied to a liquid crystal display apparatus.
With such a liquid crystal display apparatus, in recent years, the mainstream of high pixel standard has advanced to increase in the number of pixels such as from the XGA (1024×768) standard to the SXGA+ (1400×1050) standard, and also the mainstream of frame rate has advanced to increase such as from 60 Hz to 120 Hz, and further to 240 Hz, as a measure against flickering and so forth, and consequently, there has been demand for speeding up of digital signal processing circuits for performing signal processing.
For example, the master clock (driving frequency) in the case of XGA is 65 MHz, and the master clock in the case of SXGA+ is 108 MHz. However, the operating speed of a digital signal processing circuit has a limit, such that a digital signal processing IC cannot operate when the master clock is excessively high, noise is increased by spurious emissions due to a high-frequency clock, and so forth, and consequently, it is difficult for a digital signal processing circuit to operate with the master clock in the case of SXGA+. Accordingly, with liquid crystal display apparatuses, the master clock of each of the digital signal processing circuits is decreased by performing parallel processing within a single digital signal processing IC, or by performing parallel processing using multiple digital signal processing ICs, thereby handling the speeding up thereof.
Also, the writing speed of a liquid crystal display apparatus is not so fast as a picture signal to be input can be written one dot (pixel) at a time in order, so a writing method for writing multiple pixels at a time in parallel in the horizontal direction has been employed in general, and multiple S/H drivers have been sometimes employed depending on the screen resolution of a the liquid crystal display apparatus.
As described above, in order to handle increase in the number of pixels and increase in a frame rate, with a liquid crystal display apparatus, multiple digital signal processing circuits, and multiple S/H drivers, are employed and connected thereto, but in this case, the wiring between the digital signal processing circuits, S/H drivers, and the liquid crystal display apparatus, will be determined inevitably.
FIG. 1 is a diagram illustrating a configuration example of an existing liquid crystal display system. The example in FIG. 1 illustrates an example in the case of employing two DSDICs as digital signal processing circuits, and RGT=H represents that this case is not mirror reversed display but normal display.
The liquid crystal display system in FIG. 1 is made up of a scan converter 11, DSDICs 12-1 and 12-2, S/H drivers 13-1 and 13-2, and a liquid crystal apparatus 14. Note that with the example in FIG. 1, the DSDIC 12-1 serves as a master, and the DSDIC 12-2 serves as a slave, so hereafter, which will be simply referred to as a master IC 12-1 and a slave IC 12-2, respectively.
The scan converter 11 subjects an analog picture signal input from an unshown previous stage to A/D (Analog/Digital) conversion, number-of-pixel conversion, number-of-line conversion, frequency conversion, or the like, and alternately inputs a digital picture signal after conversion to the master IC 12-1 and the slave IC 12-2. That is to say, the odd data of a picture signal (the 1st, 3rd, 5th, 7th, 9th, and 11th data) is input to the master IC 12-1, and the even data of a picture signal (the 2nd, 4th, 6th, 8th, 10th, and 12th data) is input to the slave IC 12-2.
The master IC 12-1 subjects the input odd data to predetermined signal processing, and outputs a signal SIG1 after the signal processing (the 1st, 3rd, 5th, 7th, 9th, and 11th data) to the S/H driver 13-1. Also, the master IC 12-1 supplies clock CLKOUT1 to the S/H driver 13-1, and also generates a timing pulse for driving, and supplies the generated timing pulse to the S/H driver 13-1, S/H driver 13-2, and liquid crystal display apparatus 14.
The slave IC 12-2 subjects the input even data to predetermined signal processing, and outputs a signal SIG2 after the signal processing (the 2nd, 4th, 6th, 8th, 10th, and 12th data) to the S/H driver 13-2. Also, the slave IC 12-2 supplies clock CLKOUT2 to the S/H driver 13-2.
The S/H driver 13-1 inputs, as shown by dotted lines, based on the clock CLKOUT1 from the master IC 12-1, the signal SIG1 (the 1st, 3rd, 5th, 7th, 9th, and 11th data equivalent to six pixels of the liquid crystal display apparatus 14) to the 1st, 3rd, 5th, 7th, 9th, and 11th pixels, which are the horizontal display positions of the liquid crystal display apparatus 14, from the top in the drawing simultaneously.
Based on the clock CLKOUT2 from the slave IC 12-2, the S/H driver 13-2 inputs, as shown by solid lines, the signal SIG2 (the 2nd, 4th, 6th, 8th, 10th, and 12th data equivalent to six pixels of the liquid crystal display apparatus 14) to the 2nd, 4th, 6th, 8th, 10th, and 12th pixels, which are the horizontal display positions of the liquid crystal display apparatus 14, from the top in the drawing simultaneously.
With the liquid crystal display apparatus 14, the pixels are disposed in a matrix shape, and for example, a liquid crystal panel employing a 12-pixel simultaneous writing system for writing 12 pixels in parallel can be employed. With the example in FIG. 1, in order from the top in the drawing, 12 pixels from the first pixel in order in the horizontal direction are illustrated. Note that a number illustrated on each of the pixels represents a data number of a signal to be written in each of the pixels.
The liquid crystal display apparatus 14 writes the signal SIG1 from the S/H driver 13-1 and the signal SIG2 from the S/H driver 13-2 each six pixels at a time in parallel in the horizontal direction based on the timing pulse from the master IC 12-1. At this time, the 1st, 3rd, 5th, 7th, 9th, and 11th data of the signal SIG1 from the S/H driver 13-1 are written in the 1st, 3rd, 5th, 7th, 9th, and 11th pixels from the top of the liquid crystal display apparatus 14, and also the 2nd, 4th, 6th, 8th, 10th, and 12th data of the signal SIG2 from the S/H driver 13-2 are written in the 2nd, 4th, 6th, 8th, 10th, and 12th pixels from the top of the liquid crystal display apparatus 14.
As described above, in the event that the horizontal display positions of the liquid crystal display apparatus 14 are in a default state (HP (Horizontal Position)=default), the 1st through 12th data from the S/H drivers 13-1 and 13-2 are written in the pixels of the liquid crystal display apparatus 14 in order from the top in the drawing. That is to say, in the case of the example in FIG. 1, the wiring between the S/H drivers 13-1 and 13-2 and the liquid crystal display apparatus 14 has been determined such that the data to be written in the odd-numbered pixels of the liquid crystal display apparatus 14 are input from the S/H driver 13-1, and the data to be written in the even-numbered pixels of the liquid crystal display apparatus 14 are input from the S/H driver 13-2.
Thus, in the event of connecting multiple digital signal processing circuits and multiple S/H drivers to a liquid crystal display apparatus, the wiring between the digital signal processing circuits and the S/H drivers and the liquid crystal display apparatus is determined inevitably, so upon the horizontal display positions being moved by one position from the default state, multiple pixels (two pixels in the case of FIG. 1) are moved inevitably, as shown in the arrow at the right side.
That is to say, in the event of moving the horizontal display positions of the liquid crystal display apparatus 14 by one position (HP=Default+1), the 3rd through 14th data of the S/H drivers 13-1 and 13-2 are written in the pixels of the liquid crystal display apparatus 14 in order from the top in the drawing. Accordingly, in the event of moving the horizontal display positions in increments of one pixel (dot), as shown in FIG. 2, the data to be input to the master IC 12-1 and the data to be input the slave IC 12-2 from the scan converter 11 need to be interchanged to shift the data to be input to the slave IC 12-2 by one piece of data.
FIG. 2 illustrates an example of a case in which with the liquid crystal display system in FIG. 1, the data to be input to the master IC 12-1 and the data to be input to the slave IC 12-2 are interchanged. That is to say, in the case of the example in FIG. 2, the even data of the picture signal from the scan converter 11 (the 2nd, 4th, 6th, 8th, 10th, and 12th data) from the scan converter 11 is input to the master IC 12-1, and the odd data of the picture signal (the 1st, 3rd, 5th, 7th, 9th, and 11th data) is input to the slave IC 12-2.
Accordingly, as shown by the dotted lines, the S/H driver 13-1 inputs the signal SIG1 (the 2nd, 4th, 6th, 8th, 10th, and 12th data) from the master IC 12-1 to the 1st, 3rd, 5th, 7th, 9th, and 11th pixels from the top of the liquid crystal display apparatus 14 simultaneously.
As shown by the solid lines, the S/H driver 13-2 inputs the signal SIG2 (the 3rd, 5th, 7th, 9th, 11th, and 13th data) from the slave IC 12-2 to the 2nd, 4th, 6th, 8th, 10th, and 12th pixels from the top of the liquid crystal display apparatus 14 simultaneously.
According to the above-mentioned arrangement, in the event that the horizontal display positions of the liquid crystal display apparatus 14 in FIG. 2 are in a default state (HP (Horizontal Position)=default), the 3rd through 13th data from the S/H drivers 13-1 and 13-2 are written in the pixels of the liquid crystal display apparatus 14 in order from the top in the drawing. Thus, interchanging and shifting between the data to be input to the master IC 12-1 and the data to be input to the slave IC 12-2 from the scan converter 11 are performed, whereby the horizontal display positions of the liquid crystal display apparatus 14 in FIG. 1 can be shifted by one dot.
Also, with the liquid crystal display system in FIG. 1, even in the event of performing mirror reversed display, as shown in FIG. 3, the data to be input to the master IC 12-1 and the data to be input to the slave IC 12-2 from the scan converter 11 need to be interchanged.
FIG. 3 illustrates an example of a case in which with the liquid crystal display system in FIG. 1, mirror reversed display (RGT=L) is set, and also the data to be input to the master IC 12-1 and the data to be input to the slave IC 12-2 are interchanged. That is to say, in the case of the example in FIG. 3, the even data of the picture signal from the scan converter 11 (the 2nd, 4th, 6th, 8th, 10th, and 12th data) is input to the master IC 12-1, and the odd data of the picture signal (the 1st, 3rd, 5th, 7th, 9th, and 11th data) is input to the slave IC 12-2.
Accordingly, as shown by dotted lines, the S/H driver 13-1 inputs the signal SIG1 (the 2nd, 4th, 6th, 8th, 10th, and 12th data) from the master IC 12-1 in reverse order to the 1st, 3rd, 5th, 7th, 9th, and 11th pixels from the top in the drawing of the liquid crystal display apparatus 14 simultaneously.
As shown by solid lines, the S/H driver 13-2 inputs the signal SIG2 (the 1st, 3rd, 5th, 7th, 9th, and 11th data) from the slave IC 12-2 in reverse order to the 2nd, 4th, 6th, 8th, 10th, and 12th pixels from the top in the drawing of the liquid crystal display apparatus 14 simultaneously.
According to the above-mentioned arrangement, in the event that the horizontal display positions of the liquid crystal display apparatus 14 in FIG. 3 are in a default state (HP (Horizontal Position)=default), the 12th through 1st data from the S/H drivers 13-1 and 13-2 are written in the pixels of the liquid crystal display apparatus 14 in order from the top in the drawing. Thus, interchanging between the data to be input to the master IC 12-1 and the data to be input to the slave IC 12-2 from the scan converter 11 is performed, whereby the horizontal display positions of the liquid crystal display apparatus 14 in FIG. 1 can be subjected to mirror reversed display.
Now, for example, with the invention described in Japanese Unexamined Patent Application Publication No. 2002-111249, a single digital signal processing circuit performs multiple inputs, and multiple simultaneous processes, and the movement of the horizontal display positions in increments of single dots is realized by interchanging ports at the time of input or output.
FIG. 4 illustrates a configuration example of a liquid crystal display system in the case of performing the interchanging of ports. The liquid crystal display system shown in FIG. 4 differs from the liquid crystal display system in that the DSDICs 12-1 and 12-2 are replaced with a DSDIC 21, but it is common to both that the scan converter 11, S/H drivers 13-1 and 13-2, and liquid crystal display apparatus 14 are provided.
Specifically, the scan converter 11 inputs the odd data of a picture signal (the 1st, 3rd, 5th, 7th, 9th, and 11th data) and the even data of a picture signal (the 2nd, 4th, 6th, 8th, 10th, and 12th data) to the two input ports of the DSDIC 21, respectively.
The DSDIC 21 is made up of a port interchanging unit 31, a signal processing unit 32, and a port interchanging unit 33. The port interchanging units 31 and 33 interchange output ports so as to output the odd data and even data input from each input port to an output port for the S/H driver 13-1 or an output port for the S/H driver 13-2.
The signal processing unit 32 subjects two systems of data input from the port interchanging unit 31 to signal processing in parallel, and outputs the signals subjected to the signal processing to the port interchanging unit 33. Also, the signal processing unit 32 supplies clock CLKOUT1 and clock CLKOUT2 to the S/H drivers 13-1 and 13-2 respectively, and also generates a timing pulse for driving, and supplies the generated timing pulse to the S/H drivers 13-1 and 13-2, and the liquid crystal display apparatus 14.
Accordingly, the signal SIG1 made up of one data set of the data set of the 1st, 3rd, 5th, 7th, 9th, and 11th data, and the data set of the 2nd, 4th, 6th, 8th, 10th, and 12th data is output from the DSDIC 21 to the S/H driver 13-1, and the signal SIG2 made up of the other data set (which differs from the data set of the signal SIG1) of the data set of the 2nd, 4th, 6th, 8th, 10th, and 12th data, and the data set of the 1st, 3rd, 5th, 7th, 9th, and 11th data is output to the S/H driver 13-2.
For example, in the event that the signal SIG1 is made up of the data set of the 1st, 3rd, 5th, 7th, 9th, and 11th data, and the signal SIG2 is made up of the data set of the 2nd, 4th, 6th, 8th, 10th, and 12th data, as shown by the dotted lines, the S/H driver 13-1 inputs the signal SIG1 (the 1st, 3rd, 5th, 7th, 9th, and 11th data) from the DSDIC 21 to the 1st, 3rd, 5th, 7th, 9th, and 11th pixels from the top in the drawing of the liquid crystal display apparatus 14 simultaneously. As shown by the solid lines, the S/H driver 13-2 inputs the signal SIG2 (the 2nd, 4th, 6th, 8th, 10th, and 12th data) from the DSDIC 21 to the 2nd, 4th, 6th, 8th, 10th, and 12th pixels from the top in the drawing of the liquid crystal display apparatus 14 simultaneously.
According to the above-mentioned arrangement, in the event that the horizontal display positions of the liquid crystal display apparatus 14 in FIG. 3 are in a default state (HP (Horizontal Position)=default), the 1st through 12th data from the S/H drivers 13-1 and 13-2 are written in order from the top in the drawing of the liquid crystal display apparatus 14.
Note that though not shown in the drawing, according to interchanging of the ports by the port interchanging unit 31 or 33, the S/H driver 13-1 can input the signal SIG1 (the 2nd, 4th, 6th, 8th, 10th, and 12th data) from the DSDIC 21 to the 1st, 3rd, 5th, 7th, 9th, and 11th pixels from the top in the drawing of the liquid crystal display apparatus 14 simultaneously, and the S/H driver 13-2 can input the signal SIG2 (the 1st, 3rd, 5th, 7th, 9th, and 11th data) from the DSDIC 21 to the 2nd, 4th, 6th, 8th, 10th, and 12th pixels from the top in the drawing of the liquid crystal display apparatus 14 simultaneously.
As described above, with the liquid crystal display system in FIG. 4, the horizontal display positions has been able to be shifted by one dot according to a request.
Note however, the liquid crystal display system of the example in FIG. 4 is a system in the case of employing a single digital signal processing circuit, and the liquid crystal display system of the example in FIG. 4 has not been able to handle the case of employing multiple digital signal processing circuits.
Also, with the existing liquid crystal display system, in the case of employing multiple digital signal processing circuits, unless data is interchanged in the previous stage wherein a picture signal is input to the digital signal processing circuits, the movement of the horizontal display positions in increments of single dots has not been able to be performed, and further with regard to correction functions in which the precision in increments of single dots is required, such as a luminescent-spot correction function, a color unevenness correction function shown in Japanese Unexamined Patent Application Publication No. 2000-122023, a sharpness function, and a vertical stripe correction function as well, the precision has resulted in a multiple-dots unit (two dots in the case of employing two digital signal processing circuits), and accordingly, the precision of each of the those functions has not been obtained, or those functions themselves have not been able to be used in some cases.